01

Programming Basics

  • Data types and operators
  • Conditional and looping constructs
  • Data structures

02

Getting Started

  • Introduction to VLSI
  • Simulators
  • Shell scripting
  • Linux commands

03

Digital Fundamentals

  • Combinational circuit design
  • Sequential circuit Design
  • State machine design

04

Verilog Language

  • Introduction to Verilog
  • Structure of a Verilog
  • Data types
  • Operators
  • Procedural blocks
  • Conditional,Looping Statement

05

Verilog for Design

  • Synthesizable constructs
  • Combinational design
  • Sequential design
  • Synchronous and asynchronous design
  • Finite State Machine

06

Verilog for Verification

  • Verilog Testbench Design
  • Events and delays
  • Clock and reset generation
  • Tasks and functions
  • Testcases
  • Checkers and scoreboarding
  • Testplan creation

07

System Verilog

  • Data Types
  • Classes
  • Interfaces
  • Randomization
  • Assertions
  • Coverage

08

UVM

  • Introduction to UVM
  • UVM architecture
  • UVM Phases
  • TLM
  • UVC design (Driver, monitor, sequencer and agents)
  • Sequences and testcases
  • Configuration database
  • Callbacks
  • UVM testbench design

09

Verification Project flow

  • Verification environment
  • Architecture
  • Feature list
  • Coverage plan
  • Tracking project progress
  • Regression
  • Coverage analysis

10

Project Work

  • Projects in Verilog, System Verilog and UVM
  • VIP development

11

Soft Skills

  • E-mail communication
  • Presentations
  • Documentation
  • Mock interviews