01
System Verilog
- Data Types
- Classes
- Interfaces
- Randomization
- Assertions
- Coverage
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02
UVM
- Introduction to UVM
- UVM architecture
- UVM Phases
- TLM
- UVC design (Driver, monitor, sequencer and agents)
- Sequences and testcases
- Configuration database
- Callbacks
- UVM testbench design
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03
Verification Project flow
- Verification environment
- Architecture
- Feature list
- Coverage plan
- Tracking project progress
- Regression
- Coverage analysis
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05
Project Work
- Projects in Verilog, System Verilog and UVM
- VIP development
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05
Soft Skills
- E-mail communication
- Presentations
- Documentation
- Mock interviews
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