01

System Verilog

  • Data Types
  • Classes
  • Interfaces
  • Randomization
  • Assertions
  • Coverage

02

UVM

  • Introduction to UVM
  • UVM architecture
  • UVM Phases
  • TLM
  • UVC design (Driver, monitor, sequencer and agents)
  • Sequences and testcases
  • Configuration database
  • Callbacks
  • UVM testbench design

03

Verification Project flow

  • Verification environment
  • Architecture
  • Feature list
  • Coverage plan
  • Tracking project progress
  • Regression
  • Coverage analysis

05

Project Work

  • Projects in Verilog, System Verilog and UVM
  • VIP development

05

Soft Skills

  • E-mail communication
  • Presentations
  • Documentation
  • Mock interviews